mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 936

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
38.4.8 SPI Baud Rate Generation
As shown in the following figure, the clock source for the SPI baud rate generator is the
bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1,
2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR3:SPR2:SPR1:SPR0) divide the output
of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, 256, or 512 to get the internal SPI master
mode bit-rate clock.
The baud rate generator is activated only when the SPI is in the master mode and a serial
transfer is taking place. In the other cases, the divider is disabled to decrease I
The baud rate divisor equation is as follows (except those reserved combinations in the
SPI Baud Rate Divisor table).
BaudRateDivisor = (SPPR + 1) × 2
The baud rate can be calculated with the following equation:
BaudRate = BusClock / BaudRateDivisor
38.4.9 Special Features
The following section shows the module special features.
38.4.9.1 SS Output
The SS output feature automatically drives the SS pin low during transmission to select
external devices and drives the SS pin high during idle to deselect external devices. When
the SS output is selected, the SS output pin is connected to the SS input pin of the
external device.
The SS output is available only in master mode during normal SPI operation by asserting
the SSOE and MODFEN bits as shown in the description of the C1[SSOE] bit.
The mode fault feature is disabled while SS output is enabled.
936
CLOCK
BUS
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 38-40. SPI Baud Rate Generation
SPPR2:SPPR1:SPPR0
1, 2, 3, 4, 5, 6, 7, or 8
PRESCALER
DIVIDE BY
(SPR + 1)
Preliminary
SPR3:SPR2:SPR1:SPR0
2, 4, 8, 16, 32, 64, 128,
BAUD RATE DIVIDER
256, or 512
DIVIDE BY
Freescale Semiconductor, Inc.
MASTER
SPI
BIT RATE
DD
current.