mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 336

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Introduction
15.1.3 Modes of Operation
The CF1_INTC module does not support any special modes of operation. As a memory-
mapped slave peripheral located on the platform's slave bus, it responds based strictly on
the memory addresses of the connected bus.
One special behavior of the CF1_INTC deserves mention. When the device enters a wait
or stop mode and certain clocks are disabled, there is an input signal that can be asserted
to enable a purely-combinational logic path for monitoring the assertion of an interrupt
request. After a request of unmasked level is asserted, this combinational logic path
asserts an output signal that is sent to the clock generation logic to re-enable the internal
device clocks to exit the low-power mode.
15.1.4 Device-Specific Exception and Interrupt Vector Tables
Refer to the Chip Configuration details for this information.
336
• Support of 30 peripheral I/O interrupt requests plus seven software (one per level)
• Fixed association between interrupt request source and level plus priority
• Unique vector number for each interrupt source
• Support for service routine interrupt acknowledge (software IACK) read cycles for
• Combinatorial path provides wakeup signal from wait and stop modes
• Ability to mask any individual interrupt source, plus global mask-all capability
interrupt requests
improved system performance
• 30 I/O requests assigned across seven available levels and nine priorities per
• Exactly matches HCS08 interrupt request priorities
• Up to two requests can be remapped to the highest maskable level + priority
• ColdFire vector number = 62 + HCS08 vector number
• Details on IRQ and vector assignments are device-specific
level
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.