mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1203

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

46.4.3.1 Edge only sensitivity
A valid edge on an enabled pin interrupt sets an associated PTIF bit. If the PTDMAEN
bit in the IC register is set, a DMA request is asserted. If the PTDMAEN bit is not set and
the PTIE bit is set, an interrupt request is presented to the CPU. Clearing a PTIF bit is
accomplished by writing 1 to the same bit or when the DMA DONE signal for a pin
DMA request is asserted.
46.4.3.2 Edge and level sensitivity
A valid edge or level on a pin enabled for pin interrupt sets an associated PTIF bit. If the
PTDMAEN bit in the IC register is set, a DMA request is asserted. If the PTDMAEN bit
is not set and the PTIE bit is set, an interrupt request is presented to the CPU. Clearing a
PTIF bit is accomplished by writing 1 to the same bit or when the DMA DONE signal for
a pin DMA request is asserted, provided the associated enabled input of the pin interrupt
is at its negated level. During an attempt to clear a PTIF bit, if the associated pin enabled
for pin interrupt is asserted, the PTIF bit remains set. Because the DMA process is
automatic and negating all enabled inputs before the DMA DONE signal is done is very
difficult, it is strongly recommended not to enable a pin DMA request when both edge
and level are selected as valid conditions for pin interrupt (the corresponding PTMOD bit
is 1).
46.4.3.3 Control of pullup/pulldown resistors
The enabled pin interrupt can be configured to use an internal pullup/pulldown resistor
with the associated I/O port pulling enable register. When an internal pulling resistor is
enabled (the pin is configured as an input and the PTPUE bit is 1), three situations can
apply:
Freescale Semiconductor, Inc.
1. If the EGPIO gets control of the pin and the pin is enabled for pin interrupt, the
2. If the EGPIO does not get control of the pin or if the pin is not enabled for pin
3. If the EGPIO does not get control of the pin and the pin is still enabled for pin
associated PTEDG bit in the IES register selects whether the resistor is a pullup (the
PTEDG bit is 0) or a pulldown (the PTEDG bit is 1).
interrupt, the PTEDG bits have no effect.
interrupt, the PTEDG bits have no effect on selecting pullup/pulldown resistors.
Nevertheless, the value of the associated PTEDG bit must match the pullup/pulldown
selection on the pad as defined by the module that gets control of the pin: if the
module's actual selection is an internal pullup, the PTEDG bit must be cleared, and if
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 46 Enhanced GPIO (EGPIO)
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