mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1049

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

42.4.6.1 Byte Transfer Interrupt
The transfer complete flag (TCF) bit is set at the falling edge of the ninth clock to
indicate the completion of a byte and acknowledgement transfer. When FACK is enabled,
TCF is then set at the falling edge of 8th clock to indicate the completion of byte.
42.4.6.2 Address Detect Interrupt
When the calling address matches the programmed slave address (I2C Address Register)
or when the GCAEN bit is set and a general call is received, the IAAS bit in the Status
Register is set. The CPU is interrupted, provided the IICIE bit is set. The CPU must
check the SRW bit and set its Tx mode accordingly.
42.4.6.3 Exit from Low-Power/Stop Modes
The slave receive input detect circuit and address matching feature are still active on low
power modes (wait and stop). An asynchronous input matching slave address or general
call address brings the CPU out of low power/stop mode if the interrupt is not masked.
Therefore, TCF and IAAS both can trigger this interrupt.
42.4.6.4 Arbitration Lost Interrupt
The I2C is a true multimaster bus that allows more than one master to be connected on it.
If two or more masters try to control the bus at the same time, the relative priority of the
contending masters is determined by a data arbitration procedure. The I2C module asserts
the arbitration-lost interrupt when it loses the data arbitration process and the ARBL bit
in the Status Register is set.
Arbitration is lost in the following circumstances:
Freescale Semiconductor, Inc.
1. SDA is sampled as low when the master drives high during an address or data
2. SDA is sampled as low when the master drives high during the acknowledge bit of a
3. A START cycle is attempted when the bus is busy.
4. A repeated START cycle is requested in slave mode.
5. A STOP condition is detected when the master did not request it.
transmit cycle.
data receive cycle.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 42 Inter-Integrated Circuit (I2C)
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