mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 808

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Definition
Writing any value to COUNT_H or COUNT_L updates the FTM counter with its initial
16-bit value (contained in the Counter Initial Value registers) and resets the read
coherency mechanism, regardless of the data involved in the write.
When BDM is active, the FTM counter is frozen (this is the value that you may read); the
read coherency mechanism is frozen such that the buffer latches remain in the state they
were in when the BDM became active, even if one or both counter bytes are read while
BDM is active. This assures that if you were in the middle of reading a 16-bit register
when BDM became active, it reads the appropriate value from the other half of the 16-bit
value after returning to normal execution.
Addresses: FTM0_CNTH is FFFF_8440h base + 1h offset = FFFF_8441h
37.3.5 Counter Low (FTMx_CNTL)
See the description for the Counter High register.
Addresses: FTM0_CNTL is FFFF_8440h base + 2h offset = FFFF_8442h
808
COUNT_H
COUNT_L
Reset
Field
Reset
Field
Read
7–0
Read
7–0
Write
Write
Bit
Bit
FTM1_CNTH is FFFF_8480h base + 1h offset = FFFF_8481h
FTM1_CNTL is FFFF_8480h base + 2h offset = FFFF_8482h
Counter value high byte
Counter value low byte
7
0
7
0
0
0
6
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
FTMx_CNTH field descriptions
FTMx_CNTL field descriptions
0
0
5
5
Preliminary
0
0
4
4
COUNT_H
COUNT_L
Description
Description
0
0
3
3
0
0
2
2
Freescale Semiconductor, Inc.
0
0
1
1
0
0
0
0