mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 825

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

37.3.18 Function for Linked Channels (FTMx_COMBINEn)
This register contains the control bits used to configure the fault control, synchronization,
deadtime, dual edge capture mode, complementary, and combine features of channels (n)
and (n+1).
Addresses: FTM0_COMBINE0 is FFFF_8440h base + 24h offset = FFFF_8464h
Freescale Semiconductor, Inc.
FAULTEN
Reserved
SYNCEN
Reset
Field
Read
Write
7
6
5
Bit
FTM1_COMBINE0 is FFFF_8480h base + 24h offset = FFFF_84A4h
FTM1_COMBINE1 is FFFF_8480h base + 25h offset = FFFF_84A5h
FTM1_COMBINE2 is FFFF_8480h base + 26h offset = FFFF_84A6h
FTM1_COMBINE1 is FFFF_8480h base + 25h offset = FFFF_84A5h
FTM1_COMBINE2 is FFFF_8480h base + 26h offset = FFFF_84A6h
The COMBINE0 register configures the control bits for
channels 0 and 1; COMBINE1 for channels 2 and 3;
COMBINE2 for channels 4 and 5.
The channel (n) is the even channel and the channel (n+1) is the
odd channel of a pair of channels.
This read-only bit is reserved and always has the value zero.
Fault Control Enable
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
1
Synchronization Enable
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0
1
7
0
0
The fault control in this pair of channels is disabled.
The fault control in this pair of channels is enabled.
The PWM synchronization in this pair of channels is disabled.
The PWM synchronization in this pair of channels is enabled.
FAULTEN
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
FTMx_COMBINEn field descriptions
SYNCEN
Table continues on the next page...
0
5
Preliminary
NOTE
DTEN
0
4
Description
DECAP
0
3
DECAPEN
0
2
Chapter 37 FlexTimer (FTM)
COMP
0
1
COMBINE
0
0
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