mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 653

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

29.4.1 Clock select and divide control
One of four clock sources can be selected as the clock source for the ADC module. This
clock source is then divided by a configurable value to generate the input clock to the
converter (ADCK). The clock is selected from one of the following sources by means of
the ADICLK bits.
Whichever clock is selected, its frequency must fall within the specified frequency range
for ADCK. If the available clocks are too slow, the ADC may not perform according to
specifications. If the available clocks are too fast, the clock must be divided to the
appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1,
2, 4, or 8.
29.4.2 Voltage reference selection
The ADC can be configured to accept one of the two voltage reference pairs as the
reference voltage (V
positive reference that must be between the minimum Ref Voltage High and V
ground reference that must be at the same potential as V
(V
selected using the REFSEL bits in the SC2 register. The alternate (V
voltage reference pair may select additional external pins or internal sources depending
on MCU configuration. Refer to the Chip Configuration information on the Voltage
References specific to this MCU.
Freescale Semiconductor, Inc.
• The bus clock. This is the default selection following reset.
• The bus clock divided by two. For higher bus clock rates, this allows a maximum
• ALTCLK, as defined for this MCU. Refer to the Chip Configuration information.
• The asynchronous clock (ADACK). This clock is generated from a clock source
REFH
divide by 16 of the bus clock with using the ADIV bits.
within the ADC module. Note that when the ADACK clock source is selected, it is
not required to be active prior to conversion start. When it is selected and it is not
active prior to a conversion start (ADACKEN=0), the asynchronous clock is
activated at the start of a conversion and shuts off when conversions are terminated.
In this case, there is an associated clock startup delay each time the clock source is
re-activated. To avoid the conversion time variability and latency associated with the
ADACK clock startup, set ADACKEN=1 and wait the worst case startup time of 5
µs prior to initiating any conversions using the ADACK clock source. Conversions
are possible using ADACK as the input clock source while the MCU is in Normal
Stop mode. Refer to
and V
REFL
) and alternate (V
REFSH
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Power Control
and V
REFSL
ALTH
) used for conversions. Each pair contains a
Preliminary
for more information.
and V
ALTL
). These voltage references are
Chapter 29 Analog-to-Digital Converter (ADC)
SSA
. The two pairs are external
ALTH
and V
DDA
ALTL
, and a
)
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