mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 905

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Detailed descriptions of operating modes appear in
38.1.3 Block Diagrams
This section includes block diagrams showing SPI system connections, the internal
organization of the SPI module, and the SPI clock dividers that control the master mode
bit rate.
38.1.3.1 SPI System Block Diagram
The following figure shows the SPI modules of two MCUs connected in a master-slave
arrangement. The master device initiates all SPI data transfers. During a transfer, the
master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data
in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was
in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output
from the master and an input to the slave. The slave device must be selected by a low
level on the slave select input (SS pin). In this system, the master device has configured
its SS pin as an optional slave select output.
Freescale Semiconductor, Inc.
The SPI is completely disabled in stop modes where the peripheral bus clock is
stopped and internal logic states are not retained. When the CPU wakes from these
stop modes, all SPI register content is reset.
GENERATOR
SPI SHIFTER
8 OR 16 BITS
CLOCK
MASTER
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 38-1. SPI System Connections
MOSI
MISO
SPSCK
SS
Preliminary
SPSCK
MOSI
MISO
SS
Low Power Mode
Chapter 38 Serial Peripheral Interface (SPI)
SLAVE
SPI SHIFTER
8 OR 16 BITS
Options.
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