mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1082

no-image

mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mcf51jf128VLH
Manufacturer:
MITSUBISHI
Quantity:
321
Part Number:
mcf51jf128VLH
Manufacturer:
FREESCALE
Quantity:
5 097
Part Number:
mcf51jf128VLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf51jf128VLH
Manufacturer:
FREESCALE
Quantity:
5 097
Module Memory Map
43.3.16 UART FIFO Control Register (UARTx_CFIFO)
This register provides the ability to program various control bits for FIFO operation. This
register may be read or written at any time. Note that writing the TXFLUSH and
RXFLUSH bits may result in data loss and requires careful action to prevent unintended /
unpredictable behavior, hence it is recommended that TE and RE be cleared prior to
flushing the corresponding FIFO.
Addresses: UART0_CFIFO is FFFF_8140h base + 11h offset = FFFF_8151h
1082
RXFIFOSIZE
RXFE
Field
Reset
2–0
Read
Write
3
Bit
UART1_CFIFO is FFFF_8160h base + 11h offset = FFFF_8171h
TXFLUSH
101
110
111
Receive FIFO Enable
When this bit is set the built in FIFO structure for the receive buffer is enabled. The size of the FIFO
structure is indicated by the RXFIFOSIZE field. If this bit is not set then the receive buffer operates as a
FIFO of depth one dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
cleared prior to changing this bit. Additionally TXFLUSH and RXFLUSH commands should be issued
immediately after changing this bit.
0
1
Receive FIFO. Buffer Depth
The maximum number of receive datawords that can be stored in the receive buffer before an overrun
occurs. This field is read only.
000
001
010
011
100
101
110
111
7
0
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
Transmit FIFO/Buffer Depth = 64 Datawords.
Transmit FIFO/Buffer Depth = 128 Datawords.
Reserved.
Receive FIFO/Buffer Depth = 1 Dataword.
Receive FIFO/Buffer Depth = 4 Datawords.
Receive FIFO/Buffer Depth = 8 Datawords.
Receive FIFO/Buffer Depth = 16 Datawords.
Receive FIFO/Buffer Depth = 32 Datawords.
Receive FIFO/Buffer Depth = 64 Datawords.
Receive FIFO/Buffer Depth = 128 Datawords.
Reserved.
RXFLUSH
UARTx_PFIFO field descriptions (continued)
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
0
5
Preliminary
0
4
Description
0
0
3
0
2
Freescale Semiconductor, Inc.
TXOFE
0
1
RXUFE
0
0

Related parts for mcf51jf128