mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 881

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

37.4.16 Initialization
The initialization forces the CHnOI bit value to the channel (n) output when a one is
written to the INIT bit.
37.4.17 Features Priority
The following figure shows the priority of the features that can be combined to generate
channel (n) and (n+1) outputs.
37.4.18 Channel Trigger Output
The channel trigger output is generated if (FTMEN = 1) and (one or more channels were
selected by the CHjTRIG bit, where j = 0, 1, 2, 3, 4, or 5). The CHjTRIG bit defines if
the channel (j) match (that is, FTM counter = C(j)VH:L) generates the trigger.
The channel trigger output provides a trigger signal that is used for on-chip modules.
The FTM is able to generate multiple triggers in one PWM period. Since each trigger is
generated for a specific channel several channels are required to implement this
functionality. This behavior is described in the following figure.
Freescale Semiconductor, Inc.
in Output Compare, EPWM,
Output modes logic
CPWM, Combine and/or
Complementary modes)
(generation of channels
(n) and (n 1) output
Polarity control is only available in combine mode.
• It is recommended using the initialization only when the
• Initialization is only available in combine mode.
FTM counter is disabled (CLKS[1:0] = 0:0).
Deadtime
Insertion
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 37-203. FTM Features Priority
Initialization
Preliminary
Note
Note
Output
Mask
Control
Fault
Polarity
Control
Chapter 37 FlexTimer (FTM)
channel (n
channel (n) output
1) output
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