mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1286

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
automatically generate a system reset. Some of these fault types include illegal
instructions, privilege errors, address errors, and bus error terminations, with the response
under control of the processor's CPUCR[ARD, IRD] bits.
1286
Fault-on-fault
Hardware
breakpoint
trigger
HALT instruction
BACKGROUND
command
Halt Source
Halt Timing
Immediate
Immediate
Pending
Pending
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Refers to the occurrence of any fault while exception processing. For example, a bus error
supervisor mode
BDM disabled or
CPUCR[ARD] =
CPUCR[ARD] =
is signaled during exception stack frame writes or while fetching the first instruction in the
flash unsecure
BDM enabled,
BDM enabled,
BDM disabled
BDM enabled
flash secure
user mode
Halt is made pending in the processor. The processor samples for pending halt and
interrupt conditions once per instruction. When a pending condition is asserted, the
Table 50-38. CPU Halt Sources
and
1
0
Table continues on the next page...
CPUCR[IRD] = 0
CPUCR[IRD] = 1 An illegal instruction exception is generated.
CPUCR[IRD] = 0
CPUCR[IRD] = 1
processor halts execution at the next sample point.
CSR[UHE] = 0
CSR[UHE] = 0
CSR[UHE] = 1
Illegal command response and BACKGROUND command is ignored.
Processor immediately halts execution at the next instruction sample
Processor is
Processor is
Preliminary
point. The processor can be restarted by a BDM GO command.
stopped
running
Execution continues at the instruction after HALT.
exception service routine.
A reset is initiated since attempted execution of an
illegal instruction
A reset event is initiated, because a privileged
instruction was attempted in user mode.
A privilege violation exception is generated.
Processor immediately halts execution at the next
instruction sample point. The processor can be
restarted by a BDM GO command. Execution
continues at the instruction after HALT.
Halt is made pending in the processor. The
processor samples for pending halt and interrupt
conditions once per instruction. When a pending
condition is asserted, the processor halts execution
at the next sample point.
Processing of the BACKGROUND command is
treated in a special manner. The processor exits the
stopped mode and enters the halted state, at which
point all BDM commands may be exercised. When
restarted, the processor continues by executing the
next sequential instruction (the instruction following
STOP).
Description
Immediately enters halt.
Reset event is initiated.
Freescale Semiconductor, Inc.