mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 925

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

An SPI transfer is initiated in the master SPI device by reading the SPI status register
(SPIx_S) when SPTEF = 1 and then writing data to the transmit data buffer (write to
SPIx_DH:SPIx_DL). When a transfer is complete, received data is moved into the
receive data buffer. The SPIx_DH:SPIx_DL registers act as the SPI receive data buffer
for reads and as the SPI transmit data buffer for writes.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI
Control Register 1 (SPIx_C1) select one of four possible clock formats to be used by the
SPI system . The CPOL bit simply selects a non-inverted or inverted clock . The CPHA
bit is used to accommodate two fundamentally different protocols by sampling data on
odd numbered SPSCK edges or on even numbered SPSCK edges .
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in
SPI control register 1 is set, master mode is selected, when the MSTR bit is clear, slave
mode is selected.
38.4.2 Master Mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module
can initiate transmissions. A transmission begins by reading the SPIx_S register while
SPTEF = 1 and writing to the master SPI data registers. If the shift register is empty, the
byte immediately transfers to the shift register. The data begins shifting out on the MOSI
pin under the control of the serial clock.
Freescale Semiconductor, Inc.
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
• SPSCK
• MOSI, MISO pin
• SS pin
• The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with
• In master mode, the function of the serial data output pin (MOSI) and the serial
the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate
register control the baud rate generator and determine the speed of the
transmission. The SPSCK pin is the SPI clock output. Through the SPSCK pin,
the baud rate generator of the master controls the shift register of the slave
peripheral.
data input pin (MISO) is determined by the SPC0 and BIDIROE control bits.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 38 Serial Peripheral Interface (SPI)
925