mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1282

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Descriptions
The DBR supports aligned and misaligned references. This table shows the relationships
between processor address, access size, and location within the 32-bit data bus.
50.3.12 Resulting Set of Possible Trigger Combinations
The resulting set of possible breakpoint trigger combinations consists of the following
options where || denotes logical OR, && denotes logical AND, and {} denotes an
optional additional trigger term:
One-level triggers of the form:
if
if
if
Two-level triggers of the form:
if
if
In these examples, PC_breakpoint is the logical summation of the PBR0/PBMR, PBR1,
PBR2, and PBR3 breakpoint registers; Address_breakpoint is a function of ABHR,
ABLR, and AATR; Data_breakpoint is a function of DBR and DBMR. In all cases, the
data breakpoints can be included with an address breakpoint to further qualify a trigger
event as an option.
The breakpoint registers can also be used to define the start and stop recording conditions
for the PST trace buffer.
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(PC_breakpoint)
(PC_breakpoint || Address_breakpoint{&& Data_breakpoint})
(Address_breakpoint {&& Data_breakpoint})
(PC_breakpoint)
then if (Address_breakpoint {&& Data_breakpoint} )
(Address_breakpoint {&& Data_breakpoint} )
then if (PC_breakpoint)
Address[1–0]
00
01
10
11
0x
1x
xx
Table 50-36. Access Size and Operand Data Location
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Access Size
Longword
Word
Word
Byte
Byte
Byte
Byte
Operand Location
Freescale Semiconductor, Inc.
D[31–24]
D[23–16]
D[31–16]
D[15–8]
D[15–0]
D[31–0]
D[7–0]