mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 814

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Definition
When BDM is active, the write coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active even if one or both
bytes of the channel value register are written while BDM is active. Any write to the CnV
registers bypasses the buffer latches and writes directly to the register while BDM is
active. The values written to the channel value registers while BDM is active are used in
output modes operation once normal execution resumes. Writes to the channel value
registers while BDM is active do not interfere with the partial completion of a coherency
sequence. After the write coherency mechanism has been fully exercised, the channel
value registers are updated using the buffered values (while BDM was not active).
Addresses: FTM0_C0VH is FFFF_8440h base + 6h offset = FFFF_8446h (refer to FTMx memory map for additional registers)
37.3.10 Channel Value Low (FTMx_CnVL)
See the description for the Channel Value High register.
Addresses: FTM0_C0VL is FFFF_8440h base + 7h offset = FFFF_8447h (refer to FTMx memory map for additional registers)
814
VAL_H
VAL_L
Reset
Field
Reset
Field
Read
7–0
Read
7–0
Write
Write
Bit
Bit
Channel Value High Byte
Captured FTM counter value of the input capture function or the match value for the output modes
Channel Value Low Byte
Captured FTM counter value of the input capture function or the match value for the output modes
7
0
7
0
0
0
6
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
FTMx_CnVH field descriptions
FTMx_CnVL field descriptions
0
0
5
5
Preliminary
0
0
4
4
VAL_H
Description
Description
VAL_L
0
0
3
3
0
0
2
2
Freescale Semiconductor, Inc.
0
0
1
1
0
0
0
0