mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 816

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Definition
37.3.12 Counter Initial Value Low (FTMx_CNTINL)
See the description for the Counter Initial Value High register.
Addresses: FTM0_CNTINL is FFFF_8440h base + 1Eh offset = FFFF_845Eh
37.3.13 Capture and Compare Status (FTMx_STATUS)
STATUS contains a copy of the status flag CHnF bit (in CnSC) for each FTM channel
for software convenience.
Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be
checked using only one read of STATUS. All CHnF bits can be cleared by reading
STATUS followed by writing 0x00 to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. CHF is
cleared by reading STATUS while CHnF is set and then writing a 0 to the CHF bit.
Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no
effect; therefore, CHF remains set indicating an event has occurred. In this case a CHF
interrupt request is not lost due to the clearing sequence for a previous CHF.
816
INIT_L
Reset
Field
Read
7–0
Write
Bit
FTM1_CNTINL is FFFF_8480h base + 1Eh offset = FFFF_849Eh
The use of STATUS register is available only when
(MODE[FTMEN] = 1), (COMBINE = 1), and (CPWMS = 0).
The use of this register with (MODE[FTMEN] = 0),
(COMBINE = 0), or (CPWMS = 1) is not recommended and its
results are not guaranteed.
Counter Initial Value Low Byte
7
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
FTMx_CNTINL field descriptions
0
5
Preliminary
NOTE
0
4
Description
INIT_L
0
3
0
2
Freescale Semiconductor, Inc.
0
1
0
0