mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 928

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
38.4.4 SPI FIFO Mode
When the FIFO feature is supported: The SPI works in FIFO mode when the
C3[FIFOMODE] bit is set. When the module is in FIFO mode, the SPI RX buffer and
SPI TX buffer are replaced by an 8-byte-deep FIFO, as the following figures show.
928
Figure 38-34. SPIH:L read side structural overview in FIFO mode
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN,
SPC0 and BIDIROE with SPC0 set FIFOMODE and
SPIMODE in slave mode will corrupt a transmission in
progress and has to be avoided.
SPI_REG_BLOCK
SPI_CORE_SHFR
MCF51JF128 Reference Manual, Rev. 2, 03/2011
FIFO Ctrlr
Read Access
Control
Load
spidh:l_rx_reg
shfr_rx_reg
Preliminary
Note
RX- FIFO
IPBus (ips_rdata[7:0])
FIFO depth = 8 bytes
SPI Data Register
Freescale Semiconductor, Inc.