mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 112

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Analog
During a low power mode of operation, where the external clock to the ADC is gated, the
ADC can also operate on an internally generated clock. In this case, after the conversion
is complete, an asynchronous interrupt can wake the system, enabling the clocks
(including the clock to the ADC) so the conversion results can be read.
3.8.2 Comparator (CMP) Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
3.8.2.1 CMP instantiation information
This chip has one high speed comparator module with an integrated 6-bit DAC and
analog mux. The CMP's 6-bit DAC sub-block supports selection of two voltage
references. For this chip, the references implemented are:
112
1. VDD: connected to the V
System memory map
Power management
Signal multiplexing
Full description
Clocking
Topic
Other peripherals
Table 3-32. Reference links to related information
Comparator (CMP)
Port mux control
Related module
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 3-25. CMP configuration
in1
input
Preliminary
Peripheral
CMP
bridge
Register
access
System memory map
Power management
Signal multiplexing
Clock distribution
Module signals
Comparator
Reference
Freescale Semiconductor, Inc.