mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 443

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

20.3.7 MCG Status Register (MCG_S)
Address: MCG_S is FFFF_8400h base + 6h offset = FFFF_8406h
Freescale Semiconductor, Inc.
IREFST
PLLST
LOCK
LOLS
Reset
Field
Read
Write
7
6
5
4
Bit
LOLS
Loss of Lock Status
This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL
output frequency has fallen outside the lock exit frequency tolerance, D
interrupt request is made when LOLS is set. LOLS is cleared by reset or by writing a logic 1 to LOLS
when LOLS is set. Writing a logic 0 to LOLS has no effect.
0
1
Lock Status
This bit indicates whether the PLL has acquired lock. Lock detection is disabled when not operating in
either PBE or PEE mode unless PLLCLKEN=1 and the MCG is not configured in BLPI or BLPE mode.
While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated
off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV[4:0] bits
in the C5 register or the VDIV[4:0] bits in the C6 register causes the lock status bit to clear and stay
cleared until the PLL has reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also
causes the lock status bit to clear and stay cleared until Stop mode is exited and the PLL has reacquired
lock. Any time the PLL is enabled and the LOCK bit is cleared, the MCGPLLCLK will be gated off until the
LOCK bit is asserted again.
0
1
PLL Select Status
This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a
write to the PLLS bit due to internal synchronization between clock domains.
0
1
Internal Reference Status
This bit indicates the current source for the FLL reference clock. The IREFST bit does not update
immediately after a write to the IREFS bit due to internal synchronization between clock domains.
0
1
7
0
PLL has not lost lock since LOLS was last cleared.
PLL has lost lock since LOLS was last cleared.
PLL is currently unlocked.
PLL is currently locked.
Source of PLLS clock is FLL clock.
Source of PLLS clock is PLL clock.
Source of FLL reference clock is the external reference clock.
Source of FLL reference clock is the internal reference clock.
LOCK
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
MCG_S field descriptions
Table continues on the next page...
PLLST
0
5
Preliminary
IREFST
1
4
Description
Chapter 20 Multipurpose Clock Generator (MCG)
0
3
CLKST
0
2
unl
. LOLIE determines whether an
OSCINIT
0
1
IRCST
0
0
443