mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1075

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Addresses: UART0_D is FFFF_8140h base + 7h offset = FFFF_8147h
Freescale Semiconductor, Inc.
Reset
Field
Read
7–0
Write
RT
Bit
UART1_D is FFFF_8160h base + 7h offset = FFFF_8167h
only needs to be read (prior to the D register) if the additional
flag data for the dataword needs to be captured.
In the normal 8-bit mode (M bit cleared) if the parity is enabled,
you get seven data bits and one parity bit. That one parity bit
will be loaded into the D register. So if you care about only the
data bits, you have to mask off the parity bit from the value you
read out of this register.
When transmitting in 9-bit data format and using 8-bit write
instructions, write first to transmit bit 8 in UART control
register 3 (C3[T8]), then D. A write to C3[T8] stores the data in
a temporary register. If D register is written first then the new
data on data bus is stored in D register, while the temporary
value (written by last write to C3[T8]) gets stored in C3[T8]
register.
Reads return the contents of the read-only receive data register and writes go to the write-only transmit
data register.
7
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
UARTx_D field descriptions
0
5
Chapter 43 Universal Asynchronous Receiver/Transmitter (UART)
Preliminary
NOTE
NOTE
0
4
Description
RT
0
3
0
2
0
1
0
0
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