mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 710

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definition
31.4.4 DAC Control Register (DACx_C0)
Addresses: DAC0_C0 is FFFF_8500h base + 21h offset = FFFF_8521h
710
DACTRGSEL
DACBFRPTF
DACBFRPBF
DACSWTRG
DACBFWMF
Reserved
DACRFS
DACEN
Field
Reset
Field
7–3
Read
Write
2
1
0
7
6
5
4
Bit
DACEN
This read-only bitfield is reserved and always has the value zero.
Reserved
DAC buffer watermark flag
0
1
DAC buffer read pointer top position flag
0
1
DAC buffer read pointer bottom position flag
0
1
DAC enable
The DACEN bit starts the Programmable Reference Generator operation.
0
1
DAC Reference Select
0
1
DAC trigger select
0
1
DAC software trigger
7
0
The DAC buffer read pointer has not reached the watermark level.
The DAC buffer read pointer has reached the watermark level.
The DAC buffer read pointer is not zero.
The DAC buffer read pointer is zero.
The DAC buffer read pointer is not equal to the DACBFUP.
The DAC buffer read pointer is equal to the DACBFUP.
The DAC system is disabled.
The DAC system is enabled.
The DAC selets DACREF_1 as the reference voltage.
The DAC selets DACREF_2 as the reference voltage.
The DAC hardware trigger is selected.
The DAC software trigger is selected.
DACRFS
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
DACTRGSEL
DACx_SR field descriptions
DACx_C0 field descriptions
Table continues on the next page...
0
5
Preliminary
DACSWTRG
0
4
0
Description
Description
LPEN
0
3
DACBWIEN
0
2
Freescale Semiconductor, Inc.
DACBTIEN
0
1
DACBBIEN
0
0