mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 398

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
17.4.5.1 STOP Mode
STOP mode is entered by executing a STOP instruction after configuring the device as
per
prior to entering stop, only the peripheral clocks are halted.
The MCG module can be configured to leave the reference clocks running.
A module capable of providing an asynchronous interrupt to the device takes the device
out of STOP mode and returns the device to normal RUN mode. Refer to the device's
Power Management chapter for peripheral, I/O, and memory operation in STOP mode.
When an interrupt request occurs, the CPU exits STOP mode and resumes processing,
beginning with the stacking operations leading to the interrupt service routine.
A system reset will cause an exit from STOP mode, returning the device to normal RUN
mode via a MCU reset.
17.4.5.2 Very Low Power Stop (VLPS) Mode
VLPS mode can be entered in one of two ways:
In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR.
A module capable of providing an asynchronous interrupt to the device takes the device
out of VLPS and returns the device to VLPR mode provided the LPWUI bit is clear.
If LPWUI is set, the device returns to normal RUN mode upon an interrupt request. The
PMSTAT register must be set to RUN before allowing the system to return to a
frequency higher than that allowed in VLPR mode.
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• Executing a STOP instruction while the MCU is in VLPR mode and STOPM=010 or
• Executing a STOP instruction while the MCU is in normal RUN mode and
Table
000 in the PMCTRL register.
STOPM=010 in the PMCTRL register. Note, when VLPS is entered directly from
RUN mode, exit to VLPR is disabled by hardware and the system will always exit
back to RUN.
17-7. In STOP mode, the bus and CPU clocks are halted. If the ENBDM is set
If neither the WAITE or STOPE bit is set when the CPU
executes a STOP instruction, the MCU will not enter either of
the stop modes. Executing a STOP instruction under this
condition results in either a system reset if the instruction-
related reset disable bit in the CPU control register is cleared
(CPUCR[IRD]=0) or an illegal instruction exception if it is set
(CPUCR[IRD]=1).
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
NOTE
Freescale Semiconductor, Inc.