mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 850

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
37.4.7 Center-Aligned PWM (CPWM) Mode
The center-aligned mode is selected when all of the following apply:
The CPWM pulse width (duty cycle) is determined by 2 × (CnVH:L – CNTINH:L) and
the period is determined by 2 × (MODH:L – CNTINH:L)(see the following figure).
MODH:L must be kept in the range of 0x0001 to 0x7FFF because values outside this
range can produce ambiguous results.
In the CPWM mode, the FTM counter counts up until it reaches MODH:L and then
counts down until it reaches CNTINH:L.
The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel
(n) match (FTM counter = CnVH:L) when the FTM counting is down (at the begin of the
pulse width) and when the FTM counting is up (at the end of the pulse width).
This type of PWM signal is called center-aligned because the pulse width centers for all
channels are aligned with the value of CNTINH:L.
The other channel modes are not compatible with the up-down counter (CPWMS = 1).
Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnVH:L registers,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by FTM.
850
• (QUADEN = 0) if the quadrature decoder feature is supported
• (DECAPEN = 0)
• (COMBINE = 0)
• (CPWMS = 1)
Figure 37-159. CPWM Period and Pulse Width with ELSnB:ELSnA = 1:0
channel (n) output
counter overflow
FTM counter =
MODH:L
MCF51JF128 Reference Manual, Rev. 2, 03/2011
channel (n) match
(FTM counting
is down)
2 x (MODH:L - CNTINH:L)
2 x (CnVH:L - CNTINH:L)
Preliminary
FTM counter =
pulse width
CNTINH:L
period
channel (n) match
(FTM counting
is up)
counter overflow
FTM counter =
MODH:L
Freescale Semiconductor, Inc.