mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1287

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

The processor's run/stop/halt status is always accessible in
XCSR[CPUHALT,CPUSTOP]. Additionally, CSR[27–24] indicate the halt source,
showing the highest priority source for multiple halt conditions. This field is cleared by a
read of the CSR. A processor halt due to the PSTB full condition as indicated by
CSR2[PSTH] is also reflected in CSR[BKPT]. The debug GO command clears CSR[26–
24] and CSR2[PSTBH].
50.4.1.2 Background Debug Serial Interface Controller (BDC)
BDC serial communications use a custom serial protocol first introduced on the
M68HC12 Family of microcontrollers and later used in the M68HCS08 family. This
protocol assumes that the host knows the communication clock rate determined by the
target BDC clock rate. The BDC clock rate may be the system bus clock frequency or an
alternate frequency source depending on the state of XCSR[CLKSW]. All
communication is initiated and controlled by the host which drives a high-to-low edge to
signal the beginning of each bit time. Commands and data are sent most significant bit
(msb) first. For a detailed description of the communications protocol, refer to
Communication
Freescale Semiconductor, Inc.
PSTB full
condition
BKGD held low
for ≥2 bus clocks
after reset
negated for POR
or BDM reset
Halt Source
Halt Timing
Immediate
Pending
Details.
Table 50-38. CPU Halt Sources (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Flash unsecure
Flash secure
PSTB
If the core is reset into a debug halt condition, the processor's response
PSTB obtrusive recording mode pends halt in the processor if the trace
overwritten). When a pending condition is asserted, the processor halts
command causes the processor to exit halted state and pass control to
processor to exit halted state and continue reset exception processing.
while it was halted. Specifically, if the PC register was loaded, the GO
commands are limited to the always-available group. A GO command
to start the processor is not allowed. The only recovery actions in this
Enters debug mode with XCSR[ENBDM, CLKSW] set. The allowable
Enters debug mode with XCSR[ENBDM, CLKSW] set. The full set of
buffer reaches its full threshold (full is defined as before the buffer is
the instruction address in the PC, bypassing normal reset exception
processing. If the PC was not loaded, the GO command causes the
Preliminary
to the GO command depends on the BDM command(s) performed
•
•
• Power cycle the device with the BKGD pin held high to reset into
Erase the flash to unsecure the memory and then proceed with
Issue a BDM reset setting CSR2[BDFR] with CSR2[BDHBR]
BDM commands is available and debug can proceed.
cleared and the BKGD pin held high to reset into normal
Description
at the next sample point.
the normal operating mode
mode are:
operating mode
debug
Chapter 50 Debug
BDM
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