mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 242

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Description
242
CBRR
BWD
Field
HAE
FSD
FHP
IME
28
27
26
25
24
23
Interrupt mask enable
Forces the processor to raise the interrupt level mask (SR[I]) to 7 during every interrupt exception.
0
1
Buffered write disable
The ColdFire core is capable of marking processor memory writes as bufferable or non-bufferable.
NOTE: If buffered writes are enabled (BWD is 0), any error status is lost as the immediate
0
1
Crossbar high priority arbitration enable
Elevates the processor's fixed crossbar arbitration from lowest to highest during the processing of
an interrupt service routine.
0
1
Flash speculation disable
This bit controls whether prefetching by the speculation buffer is enabled. When enabled,
prefetching occurs only for program flash accesses. Disabling prefetching also clears the current
prefetch buffer.
0
1
Crossbar round-robin arbitration enable
Configures the crossbar slave ports to fixed-priority or round-robin arbitration.
0
1
Crossbar force high priority arbitration.
Elevates the processor's fixed crossbar arbitration from lowest to highest.
0
1
Description
Table 11-10. CPUCR field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
termination of the data transfer assumes an error-free completion.
As part of an interrupt exception, the processor sets SR[I] to the level of the interrupt
being serviced.
As part of an interrupt exception, the processor sets SR[I] to 7. This disables all level
1-6 interrupt requests but allows recognition of the edge-sensitive level 7 requests.
Writes are buffered and the bus cycle is terminated immediately with zero wait states.
Disable the buffering of writes. In this configuration, the write transfer is terminated
based on the response time of the addressed destination memory device.
Do not enable the processor's fixed crossbar arbitration from lowest to highest during
the processing of an interrupt service routine.
Enable the processor's fixed crossbar arbitration from lowest to highest during the
processing of an interrupt service routine.
Prefetching is enabled.
Prefetching is disabled.
Fixed-priority arbitration
Round-robin arbitration
Do not force the elevation of the processor's fixed crossbar arbitration from lowest to
highest.
Force the elevation of the processor's fixed crossbar arbitration from lowest to highest.
Table continues on the next page...
Preliminary
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