mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 669

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

29.5.1.2 Pseudo-code example
In this example, the ADC module is set up with interrupts enabled to perform a single 10-
bit conversion at low power with a long sample time on input channel 1, where the
internal ADCK clock is derived from the bus clock divided by 1.
CFG1 = 0x98 (%10011000)
and V
SC2 = 0x00 (%00000000)
SC1A = 0x41 (%01000001)
RA = 0xxx
CV = 0xxx
Freescale Semiconductor, Inc.
REFL
Bit 7
Bit 6:5 ADIV
Bit 4
Bit 3
Bit 2
Bit 1:0 REFSEL
).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:2
Bit 1:0
Bit 7
Bit 6
Bit 5
Bit 4:0 ADCH
Holds results of conversion.
Holds compare value when compare function enabled.
ADLPC
ADLSMP
ACREN
DMAEN
ADACT
ADTRG
ACFE
ACFGT
COCO
AIEN
DIFF
0
1
0
00001
1
00
1
0
0
00
0
0
0
0
00
00
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Configures for low power (lowers maximum clock speed.
Sets the ADCK to the input clock ÷ 1.
Configures for long sample time.
Compare range disabled.
DMA request disabled.
Selects default voltage reference pin pair (External pins V
Read-only flag which is set when a conversion completes.
Conversion complete interrupt enabled.
Single-ended conversion selected.
Input channel 1 selected as ADC input channel.
Flag indicates if a conversion is in progress.
Software trigger selected.
Compare function disabled.
Not used in this example.
Reserved, always reads zero.
Reserved for Freescale's internal use; always write zero.
Preliminary
Chapter 29 Analog-to-Digital Converter (ADC)
REFH
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