mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 742

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
33.4.2 PDB Trigger Input Source Selection
The PDB has up to 15 trigger input sources, namely Trigger-In 0 to 14. They are
connected to on-chip or off-chip event sources. The PDB can be triggered by software
through the SC[SWTRIG]. SC[TRIGSEL] bits select the active trigger input source or
software trigger.
For the trigger input sources implemented in this MCU, refer to Chip Configuration
information.
33.4.3 DAC Interval Trigger Outputs
PDB can generate the interval triggers for DACs to update their outputs periodically.
DAC interval counter x is reset and started when a trigger input event occurs if
DACINTCx[EXT] is cleared. When the interval counter x is equal to the value set in
DACINTx register, the DAC interval trigger x output generates a pulse of one peripheral
clock cycle width to update the DACx. If DACINTCx[EXT] is set, the DAC interval
counter is bypassed and the interval trigger output x generates a pulse following the
detection of a rising edge on the DAC external trigger input. The counter and interval
trigger can be disabled by clearing the DACINTCx[TOE].
DAC interval counters are also reset when the PDB counter reaches the MOD register
value, therefore when the PDB counter rolls over to zero, the DAC interval counters
starts anew.
Together, the DAC interval trigger pulse and the ADC pre-trigger/trigger pulses allow
precise timing of DAC updates and ADC measurements. This is outlined in the typical
use case described in the following diagram.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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Freescale Semiconductor, Inc.