mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 462

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Initialization / Application Information
20.5.3.2 Example 2: Moving from PEE to BLPI Mode: MCGOUT
In this example, the MCG will move through the proper operational modes from PEE
mode with a 4 MHz crystal configured for a 48 MHz MCGOUT frequency (see previous
example) to BLPI mode with a 32 kHz MCGOUT frequency.First, the code sequence
will be described. Then a flowchart will be included which illustrates the sequence.
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1. First, PEE must transition to PBE mode:
2. Then, PBE must transition either directly to FBE mode or first through BLPE mode
3. Next, FBE mode transitions into FBI mode:
and then to FBE mode:
b. Loop until S[CLKST] are 2'b10, indicating that the external reference clock is
b. BLPE/FBE: C6 = 0x00(2'b00000000)
d. FBE: Loop until S[PLLST] is cleared, indicating that the current source for the
a. C1 = 0x90 (2'b10010000)
a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1
c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to
a. C1 = 0x54 (2'b01010100)
selected to feed MCGOUT.
FBE mode.
PLLS clock is the FLL.
• C1[CLKS] set to 2'b10 in order to switch the system clock source to the
• C6[PLLS] clear to 0 to select the FLL. At this time, with C1[FRDIV] value
Frequency =32 kHz
external reference clock.
of 2'b010, the FLL divider is set to 128, resulting in a reference frequency of
4 MHz / 128 = 31.25 kHz. If C1[FRDIV] was not previously set to 2'b010
(necessary to achieve required 31.25-39.06 kHz FLL reference frequency
with an 4 MHz external source frequency), it must be changed prior to
clearing C6[PLLS] bit. In BLPE mode,changing this bit only prepares the
MCG for FLL usage in FBE mode. With C6[PLLS] = 0, the C6[VDIV]
value does not matter.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.