mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 780

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definition
780
CMTDIV
MCGEN
EXSPC
EOCIE
BASE
Field
FSK
6–5
4
3
2
1
0
This flag is cleared by a read of the MSC register followed by an access of CMD2 or CMD4 or by the
DMA transfer.
0
1
CMT Clock Divide Prescaler
The Secondary Prescaler causes the CMT to be clocked at the IF signal frequency, or the IF frequency
divided by 2 ,4, or 8. Since these bits are not double buffered, they should not be changed during a
transmission.
00
01
10
11
Extended Space Enable
The EXSPC bit enables extended space operation.
0
1
Baseband Enable
When set, the BASE bit disables the carrier generator and forces the carrier output high for generation of
baseband protocols. When BASE is cleared, the carrier generator is enabled and the carrier output
toggles at the frequency determined by values stored in the carrier data registers. This bit is cleared by
reset. This bit is not double buffered and should not be written to during a transmission.
0
1
FSK Mode Select
The FSK bit enables FSK operation.
0
1
End of Cycle Interrupt Enable
A CPU interrupt will be requested when EOCF is set if EOCIE is high.
0
1
Modulator and Carrier Generator Enable
• The modulator is not currently active and the MCGEN bit is set to begin the initial CMT
• At the end of each modulation cycle while the MCGEN bit is set. This is recognized when a match
No end of modulation cycle occurrence since flag last cleared
End of modulator cycle has occurred
Extended space disabled
Extended space enabled
Baseband mode disabled
Baseband mode enabled
CMT operates in Time or Baseband mode
CMT operates in FSK mode
CPU interrupt disabled
CPU interrupt enabled
IF ÷ 1
IF ÷ 2
IF ÷ 4
IF ÷ 8
transmission.
occurs between the contents of the space period register and the down counter. At this time, the
counter is initialized with the (possibly new) contents of the mark period buffer, CMT_CMD1 and
CMT_CMD2, and the space period register is loaded with the (possibly new) contents of the space
period buffer, CMT_CMD3 and CMT_CMD4.
CMT_MSC field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table continues on the next page...
Preliminary
Description
Freescale Semiconductor, Inc.