mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1209

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

1. The reset values of internal registers for D are zeros. However, a read of the D register after reset returns the actual logic
47.2.2 Port Data Direction Register (PTx_DD)
Addresses: PTA_DD is FFFF_8000h base + 1h offset = FFFF_8001h
Freescale Semiconductor, Inc.
level on external pins.
PTDD[7:0]
Field
Reset
Field
Read
7–0
Write
Bit
PTB_DD is FFFF_8010h base + 1h offset = FFFF_8011h
PTC_DD is FFFF_8020h base + 1h offset = FFFF_8021h
PTD_DD is FFFF_8030h base + 1h offset = FFFF_8031h
PTE_DD is FFFF_8040h base + 1h offset = FFFF_8041h
PTF_DD is FFFF_8050h base + 1h offset = FFFF_8051h
Writes are latched into all bits of this register. When port data direction bits for port pins are set (each DD
bit is 1), reads return the last value written to this register. When a port pin is controlled by EGPIO with the
pin interrupt function disabled, an associated port data direction bit is set (the DD bit is 1). The logic level
is driven out to the corresponding MCU pin when port data direction bits for port pins are cleared (each
DD bit is 0). For pins that are configured as digital pins, reads return logic level on the pin. For port pins
that are controlled by analog functions, reads return zeros (off-value).
Port data direction bits
Each bit of the port data direction register controls whether an associated port pin is an input or output
when pin interrupt is disabled and no other module controls the pin. If the DD bit for a port pin is equal to
logic one, and Port Data Logic has control of the pin, the port pin is defined as output and the logic value
of an internal register for the D register is driven out to the corresponding MCU pin.
0
1
7
0
The port pin is defined only as an input.
The port pin is defined as an output.
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
PTx_D field descriptions (continued)
PTx_DD field descriptions
0
5
Preliminary
0
4
PTDD[7:0]
Description
Description
0
3
0
2
Chapter 47 EGPIO Port Control
0
1
0
0
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