mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1103

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 43 Universal Asynchronous Receiver/Transmitter (UART)
the data word. All necessary bit ordering is handled automatically by the module hence
the format of the data read from receive data buffer is completely independent of the
S2[MSBF] setting.
43.4.2.3 Character reception
During UART reception, the receive shift register shifts a frame in from the
unsynchronized receiver input signal. After a complete frame shifts into the receive shift
register, the data portion of the frame transfers to the UART receive buffer. Additionally,
the noise and parity error flags that are calculated during the receive process are also
captured in the UART receive buffer. The receive data buffer is accessible via the D and
C3[T8] registers. Additional received information flags regarding the receive dataword
can be read in ED register. The S1[RDRF] flag is set if the number of resulting datawords
in the receive buffer is equal to or greater than the number indicated by
RWFIFO[RXWATER]. If the C2[RIE] is also set, the RDRF flag generates an RDRF
interrupt request. Alternatively, by programming the C5[RDMAS] bit correctly a DMA
request can be generated.
When 7816E is set/enabled and C7816[TTYPE] = 0, character reception operates slightly
differently. Upon receipt of the parity bit, the validity of the parity bit is checked. If
C7816[ANACK] is set and the parity check fails or if INIT and the received character is
not a valid initial character, then a NACK is sent by the receiver. If the number of
consecutive receive errors exceeds the threshold set by ET7816[RXTHRESHOLD] then
the IS7816[RXT] flag is set and an interrupt generated if IE7816[RXTE] is set. If an error
is detected (parity or invalid initial character) the data is NOT transferred from the
receive shift register to the receive buffer. Instead, the data is overwritten by the next
incoming data.
When the C7816[ISO_7816E] is set/enabled and C7816[ONACK] is set/enabled and the
received character would result in the receive buffer overflowing a NACK is issued by
the receiver. Additionally, the S1[OR] flag is set and interrupt issued if appropriate and
the data in the shift register is discarded.
43.4.2.4 Data sampling
The receiver samples the unsynchronized receiver input signal at the RT clock rate. The
RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud
rate mismatch, the RT clock (see the following figure) is re-synchronized:
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
1103