mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1110

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional description
43.4.2.7 Hardware flow control
To support hardware flow control, the receiver can be programmed to automatically
deassert and assert RTS.
The following figure shows receiver hardware flow control functional timing. Along with
the actual character itself, RXD shows the start bit. The stop bit also indicated, with a
dashed line if necessary. The watermark is set to 2.
43.4.2.8 Baud rate tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud
rate. Accumulated bit time misalignment can cause one of the three stop bit data samples
(RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the
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• RTS will remain asserted until the transfer is completed, even if the transmitter is
• If the receiver request-to-send functionality is enabled, the receiver automatically
• The receiver asserts RTS when the number of characters in the receiver data register
• Even if RTS is deasserted, the receiver continues to receive characters until the
• If the receiver request-to-send functionality is disabled, the receiver RTS remains
disabled mid way through a data transfer, see
for more details.
deasserts RTS if the number of characters in the receiver data register is equal to or
greater than receiver data buffer's watermark, RWFIFO[RXWATER].
is less than the watermark. It is not affected by whether RDRF is asserted.
receiver data buffer is full or is overrun.
deasserted.
Figure 43-101. Receiver hardware flow control timing diagram
S1[RDRF]
Status
Register 1
read
RTS_B
MCF51JF128 Reference Manual, Rev. 2, 03/2011
data
buffer
read
RXD
C1 in reception
C1
1
Preliminary
C2
Transceiver driver enable using RTS
C1
C3
C1 C2
C3
C4
C3
Freescale Semiconductor, Inc.