mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1297

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Upon detecting the sync request from the host (which is a much longer low time than
would ever occur during normal BDC communications), the target:
The host measures the low time of this 128-cycle sync response pulse and determines the
correct speed for subsequent BDC communications. Typically, the host can determine the
correct communication speed within a few percent of the actual target speed and the
serial protocol can easily tolerate this speed error.
50.4.1.5.2 ACK_DISABLE
Disables the serial communication handshake protocol. The subsequent commands,
issued after the ACK_DISABLE command, do not execute the hardware handshake
protocol. This command is not followed by an ACK pulse.
50.4.1.5.3 ACK_ENABLE
Enables the hardware handshake protocol in the serial communication. The hardware
handshake is implemented by an acknowledge (ACK) pulse issued by the target MCU in
response to a host command. The ACK_ENABLE command is interpreted and executed
in the BDC logic without the need to interface with the CPU. However, an acknowledge
(ACK) pulse is issued by the target device after this command is executed. This feature
can be used by the host to evaluate if the target supports the hardware handshake
Freescale Semiconductor, Inc.
1. Waits for BKGD to return to a logic high.
2. Delays 16 cycles to allow the host to stop driving the high speed-up pulse.
3. Drives BKGD low for 128 BDC clock cycles.
4. Drives a 1-cycle high speed-up pulse to force a fast rise time on BKGD.
5. Removes all drive to the BKGD pin so it reverts to high impedance.
Disable host/target handshake protocol
Enable host/target handshake protocol
host
host
target
target
0x02
0x03
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MCF51JF128 Reference Manual, Rev. 2, 03/2011
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Preliminary
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Chapter 50 Debug
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