mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1185

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

46.2.2 Modes of operation
The section defines the EGPIO operation in wait, stop, and background debug modes.
Freescale Semiconductor, Inc.
• Pin interrupt
• Digital filters
• Independent internal input pulling resistor enable per pin through pulling enable
• Independent internal input pullup/pulldown select per pin through pullup/
• Independent output slew rate control per pin through slew rate enable (SRE)
• Independent output drive strength control per pin through drive strength control
• Independent input passive filter per pin through PFE register
• Pin interrupt for each pin with individual flag and individual enable bit
• Each pin is programmable as falling edge (or rising edge) only, or both falling
• One software-enabled interrupt to CPU
• One asynchronous interrupt to wake the CPU from low-power mode
• DMA interface to support transfer by DMA
• Digital filter for each pin if configured as input with individual enable bit in DFE
• Programmable digital filtering frequency through DFC register
(PUE) register
pulldown select (PUS) register
register
(DS) register
edge and low level (or both rising edge and high level) interrupt sensitivity.
register
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 46 Enhanced GPIO (EGPIO)
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