mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 232

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Introduction
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions.
The prefetched instruction stream is then gated into the two-stage operand execution
pipeline (OEP), that decodes the instruction, fetches the required operands, and then
executes the required function. Because the IFP and OEP pipelines are decoupled by an
instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in
advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
The V1 ColdFire core pipeline stages include the following:
232
• Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage)
• Two-stage operand execution pipeline (OEP)
• Instruction address generation (IAG) — Calculates the next prefetch address
• Instruction fetch cycle (IC) — Initiates prefetch on the processor's local bus
• Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects
using FIFO queue
Instruction
Execution
Operand
Pipeline
Pipeline
Fetch
DSOC
AGEX
IAG
IC
IB
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 11-1. V1 ColdFire Core Pipelines
Decode & Select,
Instruction Buffer
Operand Fetch
Generation,
Fetch Cycle
Generation
Instruction
Instruction
Address
Address
Execute
FIFO
Preliminary
Address
Read Data[31:0]
Write Data[31:0]
Freescale Semiconductor, Inc.