mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1281

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

50.3.11 Data Breakpoint and Mask Registers (DBR, DBMR)
DBR specifies data patterns used as part of the trigger into debug mode. DBR bits are
masked by setting corresponding DBMR bits, as defined in TDR.
DBR and DBMR are accessible in supervisor mode using the WDEBUG instruction and
through the BDM port using the WRITE_DREG commands.
Freescale Semiconductor, Inc.
R
W
Reset
R
W
Reset
DRc: 0x0E (DBR)
Mask
31–0
31–0
Field
Data
Field
0x0F (DBMR)
31
0
15
0
Table 50-33. Data Breakpoint and Mask Registers (DBR, DBMR)
30
0
14
0
Data breakpoint value.
Contains the value to be compared with the data value from the processor’s local bus as a
breakpoint trigger.
Data breakpoint mask
The 32-bit mask for the data breakpoint trigger.
0
1
Description
Description
29
0
13
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
0
12
0
Table 50-35. DBMR Field Descriptions
Table 50-34. DBR Field Descriptions
The corresponding DBR bit is compared to the appropriate bit of the processor’s local
data bus.
The corresponding DBR bit is ignored
27
0
11
0
26
0
10
0
Data (DBR); Mask (DBMR)
Data (DBR); Mask (DBMR)
25
0
9
0
Preliminary
24
0
8
0
23
0
7
0
22
0
6
0
21
0
5
0
20
0
4
0
Access: Supervisor write-only
19
3
0
0
18
0
2
0
Chapter 50 Debug
BDM write-only
17
0
1
0
16
0
0
0
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