mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 238

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Description
11.2.4 Condition code register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags
for results generated by processor operations. The extend bit (X) is also an input operand
during multiprecision arithmetic computations. The CCR register must be explicitly
loaded after reset and before any CMP, Bcc, or Scc instructions are executed.
238
Reset
Reset
BDM:
W
W
Field
R
R
7–5
X
4
31
15
–
–
Reset
BDM:
W
30
14
R
–
–
Table 11-4. Stack pointer registers (A7 and OTHER_A7)
Reserved; must be cleared.
Extend condition code
This bit is set to the C bit's value for arithmetic operations; otherwise not affected or set to a
specified result.
Description
29
13
–
–
7
0
0
Table 11-5. Condition code register (CCR)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
12
–
–
Table 11-6. CCR field descriptions
Store: 0xC0 (OTHER_A7)
Load: 0xE0 (OTHER_A7)
6
0
0
27
11
–
–
Table continues on the next page...
Store: 0x4F (A7)
Load: 0x6F (A7)
LSB of status register (SR)
26
10
–
–
Store: 0xCE (SR)
Load: 0xEE (SR)
5
0
0
Preliminary
25
–
9
–
24
Address
–
8
Address
–
X
4
–
23
–
7
–
22
–
6
–
N
3
–
21
–
5
–
20
–
4
–
2
Z
–
Freescale Semiconductor, Inc.
OTHER_A7: Supervisor or
19
A7: User or BDM read/
–
3
–
Access: User read/
BDM read/write
BDM read/write
1
V
–
18
–
2
–
Access:
write
write
17
–
1
–
C
0
–
16
–
0
–