mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 900

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset Overview
37.5 Reset Overview
The FTM is reset whenever any chip reset occurs.
When the FTM exits from reset:
The following figure shows the FTM behavior after the reset. At the reset (item 1), the
FTM counter is disabled (see table "FTM Clock Source Selection"), its value is updated
to zero and the pins are not controlled by FTM (table "Mode, Edge, and Level
Selection").
After the reset, the FTM should be configured (item 2). It is necessary to define the FTM
counter mode, the FTM counting limits (MODH:L and CNTINH:L registers value), the
channels mode and CnVH:L registers value according to the channels mode.
Thus, it is recommended to write any value to CNTH or CNTL registers (item 3). This
write updates the FTM counter with the CNTINH:L registers value and the channels
output with its initial value (except for channels in output compare mode)
Reset).
The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It is
important to highlight that the pins are only controlled by FTM when CLKS[1:0] bits are
different from zero (table "Mode, Edge, and Level Selection").
900
• the FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] =
• the timer overflow interrupt is zero
• the channels interrupts are zero
• the fault interrupt is zero
• the channels are in input capture mode
• the channels outputs are zero;
• the channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0b00). See table
0b00);
"Mode, Edge, and Level Selection."
MCF51JF128 Reference Manual, Rev. 2, 03/2011
(Fault
(Channel (n)
Interrupt);
(Timer Overflow
Preliminary
(Input Capture
Interrupt);
Interrupt);
Mode);
Freescale Semiconductor, Inc.
(Counter