mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 347

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

15.4.5 INTC Wakeup Control Register (INTC_WCR)
The interrupt controller provides a combinatorial logic path to generate a special wakeup
signal to exit from the wait or stop modes. The INTC_WCR register defines wakeup
condition for interrupt recognition during wait and stop modes. This mode of operation
works as follows:
Typically, the interrupt mask level loaded into the processor's status register field (SR[I])
during the execution of the stop instruction matches the INTC_WCR[MASK] value.
The interrupt controller wakeup signal is defined as:
Address: INTC_WCR is FFFF_FFC0h base + 1Bh offset = FFFF_FFDBh
Freescale Semiconductor, Inc.
1. Write to the INTC_WCR to enable this operation (set INTC_WCR[ENB]) and define
2. Execute a stop instruction to place the processor into wait or stop mode.
3. After the processor is stopped, the interrupt controller enables special logic that
4. If an active interrupt request is asserted and the resulting interrupt level is greater
the interrupt mask level needed to force the core to exit wait or stop mode
(INTC_WCR[MASK]). The maximum value of INTC_WCR[MASK] is 0x6
(0b110). The INTC_WCR is enabled with a mask level of 0 as the default after reset.
evaluates the incoming interrupt sources in a purely combinatorial path; no clocked
storage elements are involved.
than the mask value contained in INTC_WCR[MASK], the interrupt controller
asserts the wakeup output signal. This signal is routed to the clock generation logic to
exit the low-power mode and resume processing.
Reset
Field
ENB
Read
Write
7
Bit
ENB
wakeup = INTC_WCR[ENB] + (level of any asserted_int_request > INTC_WCR[MASK])
Enable wakeup signal
0
1
1
7
Wakeup signal disabled.
Enables the assertion of the combinational wakeup signal to the clock generation logic.
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
INTC_WCR field descriptions
Table continues on the next page...
0
5
0
Preliminary
0
4
Description
0
3
Chapter 15 Interrupt Controller (INTC)
0
2
MASK
0
1
0
0
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