mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 898
mcf51jf128
Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF51JF128.pdf
(1339 pages)
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Functional Description
The appropriate settings of the phase A and phase B input filters are important to avoid
glitches that may cause oscillation on the FTM counter value. The two preceding figures
show examples of oscillations that can be caused by poor input filter setup. To avoid
these oscillations, guarantee a minimum pulse width.
37.4.24 TPM Emulation
This section describe the FTM features that are selected according to the FTMEN bit.
37.4.24.1 MODH:L and CnVH:L Synchronization
If (FTMEN = 0), then the MODH:L and CnVH:L registers are updated according to the
Update of the Registers With Write Buffers
synchronization.
If (FTMEN = 1), then the MODH:L and CnVH:L registers are updated only by PWM
synchronization
37.4.24.2 Free Running Counter
If (FTMEN = 0), then the FTM counter is a free running counter when (MODH:L =
0x0000) or (MODH:L = 0xFFFF)
If (FTMEN = 1), then the FTM counter is a free running counter when (CPWMS = 0),
(CNTINH:L = 0x0000), and (MODH:L = 0xFFFF).
898
FTM counter
Figure 37-222. Motor Position Jittering Near Maximum and Minimum Count Value
CNTINH:L
MODH:L
0x0000
phase A
phase B
(PWM
Synchronization).
MCF51JF128 Reference Manual, Rev. 2, 03/2011
(Free Running
Preliminary
and they are not updated by PWM
Counter).
Freescale Semiconductor, Inc.
Time
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