mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 246

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
All ColdFire processors use an instruction restart exception model.
Exception processing includes all actions from fault condition detection to the initiation
of fetch for first handler instruction. Exception processing is comprised of four major
steps:
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1. The processor makes an internal copy of the SR and then enters supervisor mode by
2. The processor determines the exception vector number. For all faults except
3. The processor saves the current context by creating an exception stack frame on the
4. The processor calculates the address of the first instruction of the exception handler.
• A simplified exception vector table
• Reduced relocation capabilities using the vector-base register
• A single exception stack frame format
• Use of separate system stack pointers for user and supervisor modes.
setting the S bit and disabling trace mode by clearing the T bit. The interrupt
exception also forces the M bit to be cleared and the interrupt priority mask to set to
current interrupt request level.
interrupts, the processor performs this calculation based on exception type. For
interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to
obtain the vector number from the interrupt controller if CPUCR[IAE] is set. The
IACK cycle is mapped to special locations within the interrupt controller's address
space with the interrupt level encoded in the address. If CPUCR[IAE] is cleared, the
processor uses the vector number supplied by the interrupt controller at the time the
request was signaled for improved performance.
system stack. The exception stack frame is created at a 0-modulo-4 address on top of
the system stack pointed to by the supervisor stack pointer (SSP). As shown in
Figure 11-2
exceptions. The exception type determines whether the program counter placed in the
exception stack frame defines the location of the faulting instruction (fault) or the
address of the next instruction to be executed (next).
By definition, the exception vector table is aligned on a 1 MB boundary. This
instruction address is generated by fetching an exception vector from the table
located at the address defined in the vector base register. The index into the
exception table is calculated as (4 × vector number). After the exception vector has
been fetched, the vector contents determine the address of the first instruction of the
, the processor uses a simplified fixed-length stack frame for all
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.