mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 151

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

5.2.6.1 VLPR Mode Clocking
The clock dividers cannot be changed while in VLPR mode. They must be programmed
prior to entering VLPR mode to guarantee the core/system clocks are less than or equal to
2 MHz.
5.2.6.2 I
In addition to the bus clock, the I
clock generation. The maximum frequency of this clock is 50 MHz. The master clock
source can be derived from several sources. The options are external crystals OSC1 or
OSC2, external pin input, the PLL out clock with a fractional divider, or the SYSCLK
with a fractional divider. See the I
details.
5.2.6.3 USB Controller Clocking
The USB controller is a bus master attached to the crossbar switch. As such, the USB
interface clock is connected to SYSCLK.
The USB controller also requires a 48 MHz clock. The clock source options appear
below.
Freescale Semiconductor, Inc.
MCGPLLCLK or
2
S/SAI Clocking
For the USB controller to operate, the minimum interface clock
frequency is 16 MHz.
MCGFLLCLK
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 5-2. USB 48 MHz Clock Source
2
USB_CLKIN
[USBFRAC, USBDIV]
S/SAI module has different clock sources for master
2
S module's MCR and MDR register descriptions for
SIM_CLKDIV1
Preliminary
NOTE
SIM_CLKDIV1[USBSRC]
Chapter 5 Clock Distribution
USB 48 MHz
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