mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1043

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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42.4.2 10-bit Address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte.
Various combinations of read/write formats are possible within a transfer that includes
10-bit addressing.
42.4.2.1 Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed. When a 10-bit address follows a START condition,
each slave compares the first seven bits of the first byte of the slave address (11110XX)
with its own address and tests whether the eighth bit (R/W direction bit) is 0. It is
possible that more than one device finds a match and generates an acknowledge (A1).
Each slave that finds a match compares the eight bits of the second byte of the slave
address with its own address, but only one slave finds a match and generate an
acknowledge (A2). The matching slave remains addressed by the master until it receives
a STOP condition (P) or a repeated START condition (Sr) followed by a different slave
address.
Freescale Semiconductor, Inc.
(hex)
ICR
1A
1B
1C
1D
1E
1F
19
S
Table 42-68. Master-Transmitter Addresses Slave-Receiver with a 10-bit
s first 7
addres
11110
Slave
AD10
+ AD9
Divider
bits
+
SCL
112
128
144
160
192
240
96
R/W
Table 42-67. I2C Divider and Hold Values (continued)
0
Value
Hold
SDA
17
17
25
25
33
33
9
Address
MCF51JF128 Reference Manual, Rev. 2, 03/2011
A1
(Start)
Value
Hold
SCL
118
46
54
62
70
78
94
second
AD[8:1]
addres
Slave
byte
s
(Stop)
Value
Hold
SCL
121
49
57
65
73
81
97
Preliminary
A2
Data
(hex)
ICR
3A
3B
3C
3D
3E
39
3F
A
(clocks)
Divider
1536
1792
2048
2304
2560
3072
3840
Chapter 42 Inter-Integrated Circuit (I2C)
SCL
...
(clocks)
Hold
SDA
129
257
257
385
385
513
513
Data
(Start)
Value
1022
1150
1278
1534
1918
Hold
SCL
766
894
A/A
(Stop)
Value
1025
1153
1281
1537
1921
Hold
SCL
769
897
P
1043

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