mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 354

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Initialization Information
each time the encoded interrupt level changes to level 7 (regardless of the SR[I] field)
and each time the SR[I] mask changes from 7 to a lower value while the encoded request
level remains at 7.
15.6 Initialization Information
The reset state of the CF1_INTC module enables the default IRQ mappings and clears
any software-forced interrupt requests (INTC_FRC is cleared). Immediately after reset,
the CF1_INTC begins its cycle-by-cycle evaluation of any asserted interrupt requests and
forms the appropriate encoded interrupt level and vector information for the V1 ColdFire
processor core. The ability to mask individual interrupt requests using the interrupt
controller's IMR is always available, regardless of the level of a particular interrupt
request.
15.7 Application Information
This section discusses three application topics: emulation of the HCS08's one level
interrupt nesting structure, elevating the priority of two IRQs, and more details on the
operation of the software interrupt acknowledge (SWIACK) mechanism.
15.7.1 Emulation of the HCS08's 1-Level IRQ Handling
As noted in Table 10-7, the HCS08 architecture specifies a 1-level IRQ nesting
capability. Interrupt masking is controlled by CCR[I], the interrupt mask flag: clearing
CCR[I] enables interrupts, while setting CCR[I] disables interrupts. The ColdFire
architecture defines seven interrupt levels, controlled by the 3-bit interrupt priority mask
field in the status register, SR[I], and the hardware automatically supports nesting of
interrupts.
To emulate the HCS08's 1-level IRQ capabilities on V1 ColdFire, only two SR[I] settings
are used:
The ColdFire core treats the level seven requests as non-maskable, edge-sensitive
interrupts.
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• Writing 0 to SR[I] enables interrupts.
• Writing 7 to SR[I] disables interrupts.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.