mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1064

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Module Memory Map
43.3.2 UART Baud Rate Registers: Low (UARTx_BDL)
This register, along with the BDH register, controls the prescale divisor for UART baud
rate generation. To update the 13-bit baud rate setting (SBR[12:0]), first write to BDH to
buffer the high half of the new value and then write to BDL. The working value in BDH
does not change until BDL is written. BDL is reset to a non-zero value, but after reset the
baud rate generator remains disabled until the first time the receiver or transmitter is
enabled (C2[RE] or C2[TE] bits are set)
Addresses: UART0_BDL is FFFF_8140h base + 1h offset = FFFF_8141h
43.3.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system.
Addresses: UART0_C1 is FFFF_8140h base + 2h offset = FFFF_8142h
1064
Reset
Field
SBR
Reset
Read
7–0
Read
Write
Write
Bit
Bit
UART1_BDL is FFFF_8160h base + 1h offset = FFFF_8161h
UART1_C1 is FFFF_8160h base + 2h offset = FFFF_8162h
LOOPS
UART Baud Rate Bits
The baud rate for the UART is determined by these 13 bits. See
NOTE: The baud rate generator is disabled until the C2[TE] bit or the C2[RE] bit is set for the first time
NOTE: Writing to BDH has no effect without writing to BDL, since writing to BDH puts the data in a
7
0
7
0
after reset.The baud rate generator is disabled when SBR = 0.
temporary location until BDL is written.
UARTSWAI
0
0
6
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
UARTx_BDL field descriptions
RSRC
0
0
5
5
Preliminary
M
0
0
4
4
Description
SBR
WAKE
0
0
3
3
Baud rate generation
ILT
1
0
2
2
Freescale Semiconductor, Inc.
PE
0
0
1
1
for details
PT
0
0
0
0