mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1054

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Initialization/Application Information
1054
from Data reg
Dummy read
Notes:
1. If general call or SIICAEN is enabled, check to determine if the received address is a general call address (0x00) or an SMBus
2. In receive mode, one bit time delay may needed before the first and second data reading.
Clear IICIF
Switch to
Rx mode
device default address. In either case, they must be handled by user software.
Y
byte to Data reg
transmitted?
address cycle
(master Rx)?
Clear IICIF
Write next
RXAK=0?
Last byte
End of
Y
N
N
Tx
signal (MST=0)
Generate stop
N
Y
Figure 42-67. Typical I2C SMBus Interrupt Routine
Y
Tx/Rx?
Clear FACK=0
Set TXACK=1
SHTF2=1?
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SLTF or
Y
Rx
Read data from
Read data from
Delay (note 2)
Delay (note 2)
last byte to be
and soft CRC
Set TXAK to
proper value
to be read?
Clear IICIF
Last byte
and store
Data reg
Data reg
2nd to
read?
N
N
N
signal (MST=0)
Generate stop
Y
Y
Preliminary
FACK=1?
Master
mode?
RTI
Y
Read data from
Delay (note 2)
and soft CRC
Delay (note 2)
Set Tx mode
Set TXAK to
proper value
to Data reg
Clear IICIF
Write data
Data reg
(read)
N
N
N
Y
Clear ARBL
IAAS=1?
SRW=1?
interrupt routine
See typical I2C
Y
flow chart
N (write)
Read data from
Read data from
Delay (note 2)
Delay (note 2)
and soft CRC
Set TXAK to
proper value
Clear IICIF
and store
Address transfer
Data reg
Data reg
see note 1
Freescale Semiconductor, Inc.
Y
Y
Rx
from Data reg
Dummy read
Arbitration
ACK from
IAAS=1?
receiver?
Switch to
Rx mode
Tx/Rx?
lost?
Tx
N
N
N
Y
Clear IICIF
next byte
Transmit