mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1070

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Module Memory Map
1070
Field
OR
NF
FE
PF
3
2
1
0
0
1
Receiver Overrun Flag
OR is set when software fails to prevent the receive data register from overflowing with data. The OR bit
is set immediately after the stop bit has been completely received for the dataword that overflows the
buffer and all the other error flags (FE,NF and PF) are prevented from setting. The data in the shift
register is lost, but the data already in the UART data registers is not affected. If the OR flag is set, no
data will be stored in the data buffer even if sufficient room exists. Additionally, while the OR flag is set the
RDRF flag, and IDLE flags will be blocked from asserting, i.e. transition from an inactive to an active state.
To clear OR, read S1 when OR is set and then read UART data register (D). If LBKDE is enabled and a
LIN Break is detected, the OR bit will assert if the S2[LBKDIF] flag is not cleared before the next data
character is received.See
OR bit. In 7816 mode, it is possible to configure a NACK to be returned by programing the
C7816[ONACK] bit.
0
1
Noise Flag
NF is set when the UART detects noise on the receiver input. NF bit does not get set in the case of an
overrun or while the LIN break detect feature is enabled (S2[LBKDE] = 1). When NF is set, it only
indicates that a dataword has been received with noise since the last time it was cleared. There is no
guarantee that the first dataword read from the receive buffer has noise or that there is only one dataword
in the buffer that was received with noise unless the receive buffer has a depth of one. To clear NF, read
S1 and then read the UART data register (D).
0
1
Framing Error Flag
FE is set when a logic 0 is accepted as the stop bit. FE bit does not set in the case of an overrun or while
the LIN break detect feature is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
cleared. To clear FE, read S1 with FE set and then read the UART data register (D). The last data in the
receive buffer represents the data that was received with the frame error enabled. However, framing
errors are not supported when 7816E is set/enabled. However, if this flag is set, data will still not be
received in 7816 mode.
0
1
Parity Error Flag
PF is set when PE is set, S2[LBKDE] is disabled, and the parity of the received data does not match its
parity bit. The PF is not set in the case of an overrun condition. When the PF bit is set it only indicates that
a dataword was received with parity error since the last time it was cleared. There is no guarantee that the
first dataword read from the receive buffer has a parity error or that there is only one dataword in the
buffer that was received with a parity error unless the receive buffer was a depth of one. To clear PF, read
S1 and then read the UART data register (D). Within the receive buffer structure the received dataword is
tagged if it was received with a parity error. That information is available by reading the ED register prior
to reading the D register.
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
Receiver input has become idle or the flag has not been cleared since it last asserted.
No overrun has occurred since the last time the flag was cleared.
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater
than 1 then there may be data in the receiver buffer that was received with noise.
At least one dataword was received with noise detected since the last time the flag was cleared.
No framing error detected.
Framing error.
UARTx_S1 field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table continues on the next page...
Overrun (OR) flag implications
Preliminary
Description
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