mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1159

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

44.3.19 SAI MCLK Control Register (I2Sx_MCR)
The MCLK Control Register controls the clock source and direction of the Audio Master
Clock.
Addresses: I2S0_MCR is FFFF_8200h base + 100h offset = FFFF_8300h
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
Reserved
W
W
R
R
31–16
RWM
MOE
15–0
Field
Field
DUF
31
30
DUF
31
15
0
0
30
14
0
0
This read-only bitfield is reserved and always has the value zero.
Receive word mask
For each word in the frame, configures if the receive word is masked.
0
1
Divider Update Flag
Provides the status of on-the-fly updates to the MCLK Divider ratio.
0
1
MCLK Output Enable
Enables the MCLK Divider and configures the SAI_MCLK pin as an output. When software clears this bit,
this bit remains set until the MCLK divider is fully disabled.
Word N is enabled.
Word N is masked.
MCLK Divider ratio is not being updated currently.
MCLK Divider ratio is updating on-the-fly. Furthur updates to the MCLK Divider ratio are blocked while
this flag remains set.
29
13
0
0
28
12
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
0
27
11
0
0
Chapter 44 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_RMR field descriptions
I2Sx_MCR field descriptions
Table continues on the next page...
26
10
0
0
25
0
0
9
Preliminary
MICS
24
0
0
8
0
Description
Description
23
0
0
7
22
0
0
6
21
0
0
5
20
0
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1159
16
0
0
0