mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 725

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 33
Programmable Delay Block (PDB)
33.1 Introduction
The programmable delay block (PDB) provides controllable delays from either an
internal or an external trigger, or a programmable interval tick, to the hardware trigger
inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing
between ADC conversions and/or DAC updates can be achieved. The PDB can
optionally provides pulse outputs (Pulse-Out's) that are used as the sample window in the
CMP block.
33.1.1 Features
Freescale Semiconductor, Inc.
• Up to 15 trigger input sources and software trigger source
• Up to eight configurable PDB channels for ADC hardware trigger
• One PDB channel is associated with one ADC.
• One trigger output for ADC hardware trigger and up to eight pre-trigger outputs
• Trigger outputs can be enabled or disabled independently.
• One 16-bit delay register per pre-trigger output
• Optional bypass of the delay registers of the pre-trigger outputs
• Operation in One-Shot or Continuous modes
• Optional back-to-back mode operation, which enables the ADC conversions
• One programmable delay interrupt
• One sequence error interrupt
for ADC trigger select per PDB channel
complete to trigger the next PDB channel
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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