mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1274

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Descriptions
50.3.8 Trigger Definition Register (TDR)
TDR configures the operation of the hardware breakpoint logic that corresponds with the
ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers
within the debug module. TDR controls the actions taken under the defined conditions.
Breakpoint logic may be configured as one- or two-level trigger. TDR[31–16] defines the
second-level trigger, and TDR[15–0] defines the first-level trigger.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in
supervisor mode as debug control register 0x07 using the WDEBUG instruction and
through the BDM port using the WRITE_DREG command.
1274
DRc: 0x07 (TDR)
R
W
Reset
R
W
Reset
31
0
15
0
L2T
TRC
The debug module has no hardware interlocks. To prevent
spurious breakpoint triggers while the breakpoint registers are
being loaded, disable TDR (write 0 to L2EBL and L1EBL)
before defining triggers.
30
0
14
L1T
0
29
L2E
BL
0
13
L1E
BL
0
Table 50-22. Trigger Definition Register (TDR)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
0
12
0
27
0
11
0
26
0
10
0
25
L2ED
0
9
L1ED
0
Preliminary
NOTE
24
0
8
0
Second Level Trigger
First Level Trigger
23
0
7
0
22
0
6
0
21
L2DI
0
5
L1DI
0
20
0
4
0
Freescale Semiconductor, Inc.
Access: Supervisor write-only
19
L2EA
3
L1EA
0
0
18
0
2
0
BDM write-only
17
0
1
0
L2E
PC
L1E
PC
16
L2P
CI
0
0
L1P
CI
0