mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1035

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Addresses: I2C0_SMB is FFFF_81C0h base + 8h offset = FFFF_81C8h
Freescale Semiconductor, Inc.
ALERTEN
SIICAEN
TCKSEL
SHTF1
FACK
SLTF
Reset
Field
Read
Write
7
6
5
4
3
2
Bit
I2C1_SMB is FFFF_81D0h base + 8h offset = FFFF_81D8h
I2C2_SMB is FFFF_81E0h base + 8h offset = FFFF_81E8h
I2C3_SMB is FFFF_81F0h base + 8h offset = FFFF_81F8h
FACK
Fast NACK/ACK enable
For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the
result of receiving data byte.
0
1
SMBus alert response address enable
Enables SMBus alert response address.
0
1
Second I2C address enable
Enables or disables SMBus device default address
0
1
Timeout counter clock select
Selects the clock source of the timeout counter
0
1
SCL low timeout flag
This bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-
zero value (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it.
NOTE: The low timeout function is disabled when the SLT register's value is zero.
0
1
SCL high timeout flag 1
This read-only bit sets when SCL and SDA are held high more than clock × LoValue / 512, which
indicates the bus is free. This bit is cleared automatically.
7
0
An ACK or NACK is sent on the following receiving data byte
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a
data byte generates a NACK.
Disabled
Enabled
Disabled
Enabled
Bus clock / 64 frequency
Bus clock frequency
No low timeout occurs
Low timeout occurs
ALERTEN
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
I2Cx_SMB field descriptions
SIICAEN
Table continues on the next page...
0
5
Preliminary
TCKSEL
0
4
Description
SLTF
w1c
0
3
Chapter 42 Inter-Integrated Circuit (I2C)
SHTF1
0
2
SHTF2
w1c
0
1
SHTF2IE
0
0
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